Freescale Semiconductor /MKE14Z7 /SIM /MISCTRL

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Interpret as MISCTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SW_TRG)SW_TRG 0DMA_INT_SEL 0 (0)UART0ODE 0 (0)UART1ODE 0 (0)UART2ODE

UART1ODE=0, UART0ODE=0, UART2ODE=0

Description

Miscellaneous Control register

Fields

SW_TRG

Software Trigger bit to TRGMUX

DMA_INT_SEL

DMA channel interrupt OR select

UART0ODE

UART0 Open Drain Enable

0 (0): Open drain is disabled on UART0

1 (1): Open drain is enabled on UART0

UART1ODE

UART1 Open Drain Enable

0 (0): Open drain is disabled on UART1

1 (1): Open drain is enabled on UART1

UART2ODE

UART2 Open Drain Enable

0 (0): Open drain is disabled on UART2

1 (1): Open drain is enabled on UART2

Links

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